The present invention relates a manufacturing technology of a semiconductor device, for example, a technology effective when applied to a manufacturing technology of a semiconductor device having a nonvolatile memory mix-loaded therein.
Semiconductor devices having a main circuit including MISFET (metal insulator semiconductor field effect transistor) as a field effect transistor sometimes have, in addition to the main circuit for achieving the main function of the semiconductor device, an addition circuit (add-on circuit) added to the main circuit. Examples of the addition circuit include electronic fuses to be used for trimming or relief of the main circuit and memories for storing trimming information therein.
In recent years, there has been an increasing demand for an MTP (multi time program) type electronic fuse that makes use of a programmable nonvolatile memory to allow repeated adjustment. Now, as a memory for storing trimming information, used is a nonvolatile memory (NV memory) having a floating gate structure and suited for mix-loading with a field effect transistor included in a main circuit. Using such a nonvolatile memory increases the size of a memory cell so that a shift to a nonvolatile memory capable of downsizing a memory cell is under investigation. Under such a situation, using, as an addition circuit, a nonvolatile memory having a MONOS (metal oxide nitride oxide semiconductor) structure has been investigated.
Japanese Unexamined Patent Application Publication No. 2009-289823 (Patent Document 1) discloses a technology of a semiconductor integrated circuit device having, in the surface of a semiconductor substrate thereof, a peripheral circuit region and a memory cell region.
Japanese Unexamined Patent Application Publication No. Hei 5(1993)-160095 (Patent Document 2) discloses a technology of washing a semiconductor wafer with pure water added with hydrogen fluoride. Japanese Unexamined Patent Application Publication No. Hei 5(1993-235265) (Patent Document 3) discloses, in a method of manufacturing a semiconductor device, a technology having a step of washing a semiconductor wafer and a step of thermally nitriding a natural oxide film on the washed semiconductor wafer into a corresponding nitride.
[Patent Document 1] Japanese Unexamined Patent Application Publication No. 2009-289823
[Patent Document 2] Japanese Unexamined Patent Application Publication No. Hei 5(1993)-160095
[Patent Document 3] Japanese Unexamined Patent Application Publication No. Hei 5(1993)-235265